diff options
| author | Anthony Koo | 2019-02-09 02:50:51 +0100 |
|---|---|---|
| committer | Alex Deucher | 2019-03-19 21:04:03 +0100 |
| commit | 46570f090469c8c453622523ae5ccede256148f5 (patch) | |
| tree | 33c35caefc477e64a00e03fb8efd287b6473bbdd /drivers/gpu/drm/amd/display/dc/core/dc_resource.c | |
| parent | drm/amd/display: Refactor pageflips plane commit (diff) | |
| download | kernel-qcow2-linux-46570f090469c8c453622523ae5ccede256148f5.tar.gz kernel-qcow2-linux-46570f090469c8c453622523ae5ccede256148f5.tar.xz kernel-qcow2-linux-46570f090469c8c453622523ae5ccede256148f5.zip | |
drm/amd/display: Keep clocks high before seamless boot done
[Why]
UEFI boot usually uses a boot profile that uses higher clocks
and watermark settings.
UEFI boot surface is less optimal, for example it uses linear surface
[How]
Before we finish our seamless boot sequence, keep the clock and
watermark settings from boot.
Update to optimal settings only after first flip away from UEFI
frame buffer.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 0c3e8663d7b4..7f3c7defb540 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1858,6 +1858,7 @@ enum dc_status resource_map_pool_resources( struct dc_context *dc_ctx = dc->ctx; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; + struct dc_bios *dcb = dc->ctx->dc_bios; /* TODO Check if this is needed */ /*if (!resource_is_stream_unchanged(old_context, stream)) { @@ -1872,6 +1873,13 @@ enum dc_status resource_map_pool_resources( calculate_phy_pix_clks(stream); + /* TODO: Check Linux */ + if (dc->config.allow_seamless_boot_optimization && + !dcb->funcs->is_accelerated_mode(dcb)) { + if (dc_validate_seamless_boot_timing(dc, stream->sink, &stream->timing)) + stream->apply_seamless_boot_optimization = true; + } + if (stream->apply_seamless_boot_optimization) pipe_idx = acquire_resource_from_hw_enabled_state( &context->res_ctx, |