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| author | Andrew Wong | 2016-12-22 21:41:30 +0100 |
|---|---|---|
| committer | Alex Deucher | 2017-09-26 23:07:29 +0200 |
| commit | 1646a6fe746d7e923774994d2020e1707dcda884 (patch) | |
| tree | c544d0e7178f481c0d2f5eb2ceec70b9c0f2be54 /drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | |
| parent | drm/amd/display: Allow multiple instance of DTO regs (diff) | |
| download | kernel-qcow2-linux-1646a6fe746d7e923774994d2020e1707dcda884.tar.gz kernel-qcow2-linux-1646a6fe746d7e923774994d2020e1707dcda884.tar.xz kernel-qcow2-linux-1646a6fe746d7e923774994d2020e1707dcda884.zip | |
drm/amd/display: DAL3: HDR10 Infoframe encoding
- Add HDR metadata struct
- Add register programming calculations
- Added HDR metadata to surface and update_surface
- Add HDR info packet programming for DP port
Signed-off-by: Andrew Wong <andrew.wong1@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index b74a29b40a66..82133ab3224d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -518,6 +518,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets( dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); + dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); } } @@ -554,16 +555,25 @@ static void dce110_stream_encoder_update_dp_info_packets( struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); uint32_t value = REG_READ(DP_SEC_CNTL); - if (info_frame->vsc.valid) - dce110_update_generic_info_packet( + dce110_update_generic_info_packet( + enc110, + 0, /* packetIndex */ + &info_frame->vsc); + dce110_update_generic_info_packet( + enc110, + 2, /* packetIndex */ + &info_frame->spd); + dce110_update_generic_info_packet( enc110, - 0, /* packetIndex */ - &info_frame->vsc); + 3, /* packetIndex */ + &info_frame->hdrsmd); /* enable/disable transmission of packet(s). * If enabled, packet transmission begins on the next frame */ - REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); + REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); + REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); + REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); /* This bit is the master enable bit. * When enabling secondary stream engine, |