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| author | Corbin McElhanney | 2017-08-03 20:20:14 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:16:27 +0200 |
| commit | f0c4d9977ae215859ff13304ef0fc02a8b779478 (patch) | |
| tree | 42c071bfbfee2904daeb7f1db9062c47ec300105 /drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | |
| parent | drm/amd/display: log watermarks (diff) | |
| download | kernel-qcow2-linux-f0c4d9977ae215859ff13304ef0fc02a8b779478.tar.gz kernel-qcow2-linux-f0c4d9977ae215859ff13304ef0fc02a8b779478.tar.xz kernel-qcow2-linux-f0c4d9977ae215859ff13304ef0fc02a8b779478.zip | |
drm/amd/display: fix HDMI 12bits last two bits are zero issue
(FF-158) -[FF N-1] HDMI Deep Color Mode incorrect bit depth:
FMT_DYNAMIC_EXP_EN is being reset to 0
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 59925723271e..c29e51409286 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1044,14 +1044,14 @@ static enum dc_status apply_single_controller_ctx_to_hw( /* */ dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc); - pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( - pipe_ctx->stream_res.opp, - COLOR_SPACE_YCBCR601, - stream->timing.display_color_depth, - pipe_ctx->stream->signal); - /* FPGA does not program backend */ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); + pipe_ctx->stream_res.opp->funcs->opp_program_fmt( pipe_ctx->stream_res.opp, &stream->bit_depth_params, @@ -1064,6 +1064,11 @@ static enum dc_status apply_single_controller_ctx_to_hw( BREAK_TO_DEBUGGER(); return DC_ERROR_UNEXPECTED; } + pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( + pipe_ctx->stream_res.opp, + COLOR_SPACE_YCBCR601, + stream->timing.display_color_depth, + pipe_ctx->stream->signal); if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) stream->sink->link->link_enc->funcs->setup( |