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| author | Jun Lei | 2019-02-22 22:50:00 +0100 |
|---|---|---|
| committer | Alex Deucher | 2019-03-19 21:36:49 +0100 |
| commit | 33d7598d7022eac064b48e42dd4ae3e1dc9b52cd (patch) | |
| tree | 7b3c5d77a3c2063b1f1f9acd7632437466e2b5cf /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |
| parent | drm/amd/display: Expose support for alpha blending on overlays (diff) | |
| download | kernel-qcow2-linux-33d7598d7022eac064b48e42dd4ae3e1dc9b52cd.tar.gz kernel-qcow2-linux-33d7598d7022eac064b48e42dd4ae3e1dc9b52cd.tar.xz kernel-qcow2-linux-33d7598d7022eac064b48e42dd4ae3e1dc9b52cd.zip | |
drm/amd/display: fix up reference clock abstractions
[why]
"reference clock" is a very overloaded variable in DC and causes confusion
as there are multiple sources of reference clock, which may be different values
incorrect input values to DML will cause DCHUB to be programmed improperly
and lead to hard to debug underflow issues
[how]
instead of using ref clock everywhere, specify WHICH ref clock:
- xtalin
- dccg refclk
- dchub refclk
these are all distinct values which may not be equal
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index dfa5698b4ec3..5fcc69c56584 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -65,7 +65,7 @@ void print_microsec(struct dc_context *dc_ctx, struct dc_log_buffer_ctx *log_ctx, uint32_t ref_cycle) { - const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000; + const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; static const unsigned int frac = 1000; uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz; @@ -2453,7 +2453,7 @@ static void dcn10_prepare_bandwidth( hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, - dc->res_pool->ref_clock_inKhz / 1000, + dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); dcn10_stereo_hw_frame_pack_wa(dc, context); @@ -2483,7 +2483,7 @@ static void dcn10_optimize_bandwidth( hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, - dc->res_pool->ref_clock_inKhz / 1000, + dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); dcn10_stereo_hw_frame_pack_wa(dc, context); @@ -2703,7 +2703,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) struct dpp *dpp = pipe_ctx->plane_res.dpp; struct dc_cursor_mi_param param = { .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, - .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz, + .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz, .viewport = pipe_ctx->plane_res.scl_data.viewport, .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, |