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| author | Tony Cheng | 2017-07-12 17:54:10 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:15:07 +0200 |
| commit | d21becbe0225de0e2582d17d4fbc73fbd103b1f7 (patch) | |
| tree | 32987d555511dcd94b6fbcc4a54c3aa4ca5293dd /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | |
| parent | drm/amd/display: dc_validate_ctx refocunt fixes. (diff) | |
| download | kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.tar.gz kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.tar.xz kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.zip | |
drm/amd/display: avoid disabling opp clk before hubp is blanked.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 0e90e6cc4930..18686be20004 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -472,9 +472,10 @@ static void reset_front_end( struct transform *xfm = dc->res_pool->transforms[fe_idx]; struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx]; struct timing_generator *tg = dc->res_pool->timing_generators[mpcc->opp_id]; + unsigned int opp_id = mpcc->opp_id; /*Already reset*/ - if (mpcc->opp_id == 0xf) + if (opp_id == 0xf) return; tg->funcs->lock(tg); @@ -497,8 +498,12 @@ static void reset_front_end( mpcc->funcs->wait_for_idle(mpcc); - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0); - REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0); + REG_UPDATE(HUBP_CLK_CNTL[fe_idx], + HUBP_CLOCK_ENABLE, 0); + REG_UPDATE(DPP_CONTROL[fe_idx], + DPP_CLOCK_ENABLE, 0); + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); xfm->funcs->transform_reset(xfm); @@ -1211,7 +1216,12 @@ static void dcn10_power_on_fe( pipe_ctx->pipe_idx); /* enable DCFCLK current DCHUB */ - REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], HUBP_CLOCK_ENABLE, 1); + REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], + HUBP_CLOCK_ENABLE, 1); + + /* make sure OPP_PIPE_CLOCK_EN = 1 */ + REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst], + OPP_PIPE_CLOCK_EN, 1); if (dc_surface) { dm_logger_write(dc->ctx->logger, LOG_DC, |