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author | Tony Cheng | 2017-07-12 17:54:10 +0200 |
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committer | Alex Deucher | 2017-09-27 00:15:07 +0200 |
commit | d21becbe0225de0e2582d17d4fbc73fbd103b1f7 (patch) | |
tree | 32987d555511dcd94b6fbcc4a54c3aa4ca5293dd /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | |
parent | drm/amd/display: dc_validate_ctx refocunt fixes. (diff) | |
download | kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.tar.gz kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.tar.xz kernel-qcow2-linux-d21becbe0225de0e2582d17d4fbc73fbd103b1f7.zip |
drm/amd/display: avoid disabling opp clk before hubp is blanked.
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 9875d812e185..de3341d572be 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -68,14 +68,12 @@ static void set_output_mux(struct dcn10_mpcc *mpcc10, int opp_id, int mpcc_id) { ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id); mpcc10->base.opp_id = opp_id; - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1); REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id); } static void reset_output_mux(struct dcn10_mpcc *mpcc10) { REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf); - REG_UPDATE(OPP_PIPE_CONTROL[mpcc10->base.opp_id], OPP_PIPE_CLOCK_EN, 0); mpcc10->base.opp_id = 0xf; } |