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| author | Yongqiang Sun | 2017-10-30 18:35:04 +0100 |
|---|---|---|
| committer | Alex Deucher | 2017-12-06 18:47:26 +0100 |
| commit | 073a45e824db22f47940e203dc63ad081e53e9df (patch) | |
| tree | 0b6dc582c36775930d6bf0004ebb4c6967aeb190 /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | drm/amd/display: Enalbe blank data double buffer after mpc disconnected. (diff) | |
| download | kernel-qcow2-linux-073a45e824db22f47940e203dc63ad081e53e9df.tar.gz kernel-qcow2-linux-073a45e824db22f47940e203dc63ad081e53e9df.tar.xz kernel-qcow2-linux-073a45e824db22f47940e203dc63ad081e53e9df.zip | |
drm/amd/display: Add tg_init interface.
Clear OPTC underflow status when init_hw.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
3 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9b37f65f86f5..bb4446eecb39 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -742,6 +742,8 @@ static void dcn10_init_hw(struct dc *dc) hwss_wait_for_blank_complete(tg); dcn10_power_down_fe(dc, i); + + tg->funcs->tg_init(tg); } for (i = 0; i < dc->res_pool->audio_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 5d1edb017b1c..819c4edd77a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -1213,6 +1213,13 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); } +static void tgn10_tg_init(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + tgn10_set_blank_data_double_buffer(tg, true); + REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); +} static const struct timing_generator_funcs dcn10_tg_funcs = { .validate_timing = tgn10_validate_timing, @@ -1243,7 +1250,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_test_pattern = tgn10_set_test_pattern, .program_stereo = tgn10_program_stereo, .is_stereo_left_eye = tgn10_is_stereo_left_eye, - .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer + .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, + .tg_init = tgn10_tg_init, }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 395820606013..bb1cbfdc3554 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -210,6 +210,7 @@ struct dcn_tg_registers { SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ @@ -330,6 +331,7 @@ struct dcn_tg_registers { type OPTC_SRC_SEL;\ type OPTC_SEG0_SRC_SEL;\ type OPTC_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_UNDERFLOW_CLEAR;\ type OPPBUF_ACTIVE_WIDTH;\ type OPPBUF_3D_VACT_SPACE1_SIZE;\ type VTG0_ENABLE;\ |