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author | Yongqiang Sun | 2017-06-26 22:25:10 +0200 |
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committer | Alex Deucher | 2017-09-27 00:08:32 +0200 |
commit | 97416d4cbb9efab2eea7740fa4ce86b317da06c5 (patch) | |
tree | a9c242ec7db172e399fdd1ccf7ba7316c2285319 /drivers/gpu/drm/amd/display/dc/dcn10 | |
parent | drm/amd/display: Remove SMU_INTERRUPT_CONTROL (diff) | |
download | kernel-qcow2-linux-97416d4cbb9efab2eea7740fa4ce86b317da06c5.tar.gz kernel-qcow2-linux-97416d4cbb9efab2eea7740fa4ce86b317da06c5.tar.xz kernel-qcow2-linux-97416d4cbb9efab2eea7740fa4ce86b317da06c5.zip |
drm/amd/display: set drr during program timing.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index 5927478b9044..e1899f5fb083 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -177,6 +177,14 @@ static void tgn10_program_timing( REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, v_total); + /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and + * OTG_V_TOTAL_MIN are equal to V_TOTAL. + */ + REG_SET(OTG_V_TOTAL_MAX, 0, + OTG_V_TOTAL_MAX, v_total); + REG_SET(OTG_V_TOTAL_MIN, 0, + OTG_V_TOTAL_MIN, v_total); + /* v_sync_start = 0, v_sync_end = v_sync_width */ v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor; |