diff options
| author | Eric Bernstein | 2018-08-17 23:57:44 +0200 |
|---|---|---|
| committer | Alex Deucher | 2019-03-21 05:39:48 +0100 |
| commit | ae5041f3a03134a4cd5fc1c41e082c0e5d290392 (patch) | |
| tree | 9fea4c15fe52cc1203cd6d6a240afee0608815c5 /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | drm/amd/display: Move dm_read_reg_func to dc_helper. (diff) | |
| download | kernel-qcow2-linux-ae5041f3a03134a4cd5fc1c41e082c0e5d290392.tar.gz kernel-qcow2-linux-ae5041f3a03134a4cd5fc1c41e082c0e5d290392.tar.xz kernel-qcow2-linux-ae5041f3a03134a4cd5fc1c41e082c0e5d290392.zip | |
drm/amd/display: Fix setting DP_VID_N_MUL
[Why]
Need to set VID_N_MUL for 4:2:0 cases
[How]
Move setting to enc1_stream_encoder_dp_unblank and
ensure it is also set for non-4:2:0 cases.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index d370152018f8..d2a15d2e9561 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -298,7 +298,6 @@ void enc1_stream_encoder_dp_set_stream_attribute( break; case PIXEL_ENCODING_YCBCR420: dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; - REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); break; default: dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; @@ -833,13 +832,17 @@ void enc1_stream_encoder_dp_unblank( if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { uint32_t n_vid = 0x8000; uint32_t m_vid; + uint32_t n_multiply = 0; + uint64_t m_vid_l = n_vid; + + /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ + if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420) + n_multiply = 1; /* M / N = Fstream / Flink * m_vid / n_vid = pixel rate / link rate */ - uint64_t m_vid_l = n_vid; - m_vid_l *= param->pixel_clk_khz; m_vid_l = div_u64(m_vid_l, param->link_settings.link_rate @@ -859,7 +862,9 @@ void enc1_stream_encoder_dp_unblank( REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); - REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); + REG_UPDATE_2(DP_VID_TIMING, + DP_VID_M_N_GEN_EN, 1, + DP_VID_N_MUL, n_multiply); } /* set DIG_START to 0x1 to resync FIFO */ |