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| author | Eric Bernstein | 2017-10-27 00:13:36 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-12-06 18:47:25 +0100 |
| commit | bc71a20db2858739724715e5096a98692320e69f (patch) | |
| tree | 6187c56509cc9d560a63a20bc59b7d9a9d396ca0 /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | drm/amd/display: dal 3.1.11 (diff) | |
| download | kernel-qcow2-linux-bc71a20db2858739724715e5096a98692320e69f.tar.gz kernel-qcow2-linux-bc71a20db2858739724715e5096a98692320e69f.tar.xz kernel-qcow2-linux-bc71a20db2858739724715e5096a98692320e69f.zip | |
drm/amd/display: Call ipp_program_bias_and_scale only if available
Also move some register definitions to common DCN regs.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 |
2 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index 3a6ebd14eea2..880e366568a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -73,6 +73,9 @@ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ SRI(OBUF_CONTROL, DSCL, id), \ + SRI(CM_ICSC_CONTROL, CM, id), \ + SRI(CM_ICSC_C11_C12, CM, id), \ + SRI(CM_ICSC_C33_C34, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \ SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \ @@ -124,9 +127,6 @@ SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_OCSC_C11_C12, CM, id), \ SRI(CM_OCSC_C33_C34, CM, id), \ - SRI(CM_ICSC_CONTROL, CM, id), \ - SRI(CM_ICSC_C11_C12, CM, id), \ - SRI(CM_ICSC_C33_C34, CM, id), \ SRI(CM_BNS_VALUES_R, CM, id), \ SRI(CM_BNS_VALUES_G, CM, id), \ SRI(CM_BNS_VALUES_B, CM, id), \ @@ -239,6 +239,11 @@ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ + TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ + TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ + TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \ TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \ @@ -327,11 +332,6 @@ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ - TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ - TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \ - TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 90f1f54ade61..75feb4788b6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1903,7 +1903,8 @@ static void update_dchubp_dpp( //set scale and bias registers build_prescale_params(&bns_params, plane_state); - dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); + if (dpp->funcs->ipp_program_bias_and_scale) + dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params); mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; |