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| author | Dmytro Laktyushkin | 2019-03-26 18:26:37 +0100 |
|---|---|---|
| committer | Alex Deucher | 2019-06-22 16:34:08 +0200 |
| commit | 0ba37b20ef1c587a24f0f8060f32a4d56f4d65df (patch) | |
| tree | ff637d37bf364a066a3c63f63b4bf8004a6088cd /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | |
| parent | drm/amd/display: Properly set u clock (diff) | |
| download | kernel-qcow2-linux-0ba37b20ef1c587a24f0f8060f32a4d56f4d65df.tar.gz kernel-qcow2-linux-0ba37b20ef1c587a24f0f8060f32a4d56f4d65df.tar.xz kernel-qcow2-linux-0ba37b20ef1c587a24f0f8060f32a4d56f4d65df.zip | |
drm/amd/display: fix dsc validation
Currently dsc is validated not taking the image width limitation into
mind.
This change addresses that, but due to previous design being limited
to non odm dsc validation additional sequence changes are made.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index 4865cc341dec..be49fc7f4abe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -91,6 +91,8 @@ void dsc2_construct(struct dcn20_dsc *dsc, dsc->dsc_regs = dsc_regs; dsc->dsc_shift = dsc_shift; dsc->dsc_mask = dsc_mask; + + dsc->max_image_width = 5184; } @@ -161,6 +163,9 @@ static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const st { struct dsc_optc_config dsc_optc_cfg; + if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width) + return false; + return dsc_prepare_config(dsc, dsc_cfg, &dsc_optc_cfg); } |