diff options
| author | Ilya Bakoulin | 2019-04-09 17:50:38 +0200 |
|---|---|---|
| committer | Alex Deucher | 2019-06-22 16:34:10 +0200 |
| commit | fbc9ca671f4ffbc0c873de17cf2305ca438cb09e (patch) | |
| tree | 5ecb5a259a0835afca9af67e9dfa8a8fbdad71f9 /drivers/gpu/drm/amd/display/dc/dcn20 | |
| parent | drm/amd/display: Remove duplicate define of TO_DCN20_HUBBUB (diff) | |
| download | kernel-qcow2-linux-fbc9ca671f4ffbc0c873de17cf2305ca438cb09e.tar.gz kernel-qcow2-linux-fbc9ca671f4ffbc0c873de17cf2305ca438cb09e.tar.xz kernel-qcow2-linux-fbc9ca671f4ffbc0c873de17cf2305ca438cb09e.zip | |
drm/amd/display: Fix ODM combine data format
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 4 |
3 files changed, 17 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index fbcb4d860e7a..2ea72e965c1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -703,7 +703,8 @@ enum dc_status dcn20_enable_stream_timing( pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx->stream_res.tg, odm_pipe->stream_res.opp->inst, - pipe_ctx->stream->timing.h_addressable/2); + pipe_ctx->stream->timing.h_addressable/2, + pipe_ctx->stream->timing.pixel_encoding); /* HW program guide assume display already disable * by unplug sequence. OTG assume stop. */ @@ -1007,7 +1008,8 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx->stream_res.tg, combine_pipe->stream_res.opp->inst, - pipe_ctx->plane_res.scl_data.h_active); + pipe_ctx->plane_res.scl_data.h_active, + pipe_ctx->stream->timing.pixel_encoding); else pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index ea6a19063b22..d0b317ea3a7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -238,11 +238,13 @@ void optc2_set_odm_bypass(struct timing_generator *optc, OPTC_MEM_SEL, 0); } -void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive) +void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, + int mpcc_hactive, enum dc_pixel_encoding pixel_encoding) { struct optc *optc1 = DCN10TG_FROM_TG(optc); /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */ int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf; + uint32_t data_fmt = 0; /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); @@ -255,6 +257,13 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, in REG_SET(OPTC_MEMORY_CONFIG, 0, OPTC_MEM_SEL, memory_mask << (optc->inst * 4)); + if (pixel_encoding == PIXEL_ENCODING_YCBCR422) + data_fmt = 1; + else if (pixel_encoding == PIXEL_ENCODING_YCBCR420) + data_fmt = 2; + + REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt); + REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, OPTC_NUM_OF_INPUT_SEGMENT, 1, OPTC_SEG0_SRC_SEL, optc->inst, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h index a21781332a06..ebf07c582da2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h @@ -66,6 +66,7 @@ SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ @@ -95,7 +96,8 @@ void optc2_set_dsc_config(struct timing_generator *optc, void optc2_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); -void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive); +void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, + int mpcc_hactive, enum dc_pixel_encoding pixel_encoding); void optc2_get_optc_source(struct timing_generator *optc, uint32_t *num_of_src_opp, |