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| author | Alex Deucher | 2017-06-15 22:20:24 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-26 23:19:23 +0200 |
| commit | 2c8ad2d5a20c8b7425b547dd4a969ffecad29b39 (patch) | |
| tree | cd62083e903f1efe2d12b349c57466a4b5989fb1 /drivers/gpu/drm/amd/display/dc/dm_services_types.h | |
| parent | drm/amd/display: Add DCE12 core support (diff) | |
| download | kernel-qcow2-linux-2c8ad2d5a20c8b7425b547dd4a969ffecad29b39.tar.gz kernel-qcow2-linux-2c8ad2d5a20c8b7425b547dd4a969ffecad29b39.tar.xz kernel-qcow2-linux-2c8ad2d5a20c8b7425b547dd4a969ffecad29b39.zip | |
drm/amd/display: Enable DCE12 support
This wires DCE12 support into DC and enables it.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dm_services_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 460971dc3a70..8d2661583f21 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -141,6 +141,33 @@ struct dm_pp_wm_sets_with_clock_ranges { struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct dm_pp_clock_range_for_dmif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_dcfclk_clk_in_khz; + uint32_t wm_max_dcfclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_clock_range_for_mcif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_socclk_clk_in_khz; + uint32_t wm_max_socclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_wm_sets_with_clock_ranges_soc15 { + uint32_t num_wm_dmif_sets; + uint32_t num_wm_mcif_sets; + struct dm_pp_clock_range_for_dmif_wm_set_soc15 + wm_dmif_clocks_ranges[MAX_WM_SETS]; + struct dm_pp_clock_range_for_mcif_wm_set_soc15 + wm_mcif_clocks_ranges[MAX_WM_SETS]; +}; +#endif + #define MAX_DISPLAY_CONFIGS 6 struct dm_pp_display_configuration { |