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author | Dmytro Laktyushkin | 2016-12-02 00:13:25 +0100 |
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committer | Alex Deucher | 2017-09-26 23:03:01 +0200 |
commit | 9a70eba7f2c65b408ee56c7219b0cb4ae588b2bc (patch) | |
tree | 8869df81354e51392851c471e9c0abfcca805963 /drivers/gpu/drm/amd/display/dc/dm_services_types.h | |
parent | drm/amd/display: remove clocks_state enum (diff) | |
download | kernel-qcow2-linux-9a70eba7f2c65b408ee56c7219b0cb4ae588b2bc.tar.gz kernel-qcow2-linux-9a70eba7f2c65b408ee56c7219b0cb4ae588b2bc.tar.xz kernel-qcow2-linux-9a70eba7f2c65b408ee56c7219b0cb4ae588b2bc.zip |
drm/amd/display: consolidate dce8-11.2 display clock code
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dm_services_types.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dm_services_types.h | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 44bad17fa318..460971dc3a70 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -43,15 +43,17 @@ enum dm_pp_clocks_state { /* Starting from DCE11, Max 8 levels of DPM state supported. */ DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID, - DM_PP_CLOCKS_DPM_STATE_LEVEL_0 = DM_PP_CLOCKS_STATE_ULTRA_LOW, - DM_PP_CLOCKS_DPM_STATE_LEVEL_1 = DM_PP_CLOCKS_STATE_LOW, - DM_PP_CLOCKS_DPM_STATE_LEVEL_2 = DM_PP_CLOCKS_STATE_NOMINAL, + DM_PP_CLOCKS_DPM_STATE_LEVEL_0, + DM_PP_CLOCKS_DPM_STATE_LEVEL_1, + DM_PP_CLOCKS_DPM_STATE_LEVEL_2, /* to be backward compatible */ - DM_PP_CLOCKS_DPM_STATE_LEVEL_3 = DM_PP_CLOCKS_STATE_PERFORMANCE, - DM_PP_CLOCKS_DPM_STATE_LEVEL_4 = DM_PP_CLOCKS_DPM_STATE_LEVEL_3 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_5 = DM_PP_CLOCKS_DPM_STATE_LEVEL_4 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_6 = DM_PP_CLOCKS_DPM_STATE_LEVEL_5 + 1, - DM_PP_CLOCKS_DPM_STATE_LEVEL_7 = DM_PP_CLOCKS_DPM_STATE_LEVEL_6 + 1, + DM_PP_CLOCKS_DPM_STATE_LEVEL_3, + DM_PP_CLOCKS_DPM_STATE_LEVEL_4, + DM_PP_CLOCKS_DPM_STATE_LEVEL_5, + DM_PP_CLOCKS_DPM_STATE_LEVEL_6, + DM_PP_CLOCKS_DPM_STATE_LEVEL_7, + + DM_PP_CLOCKS_MAX_STATES }; struct dm_pp_gpu_clock_range { |