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| author | Zeyu Fan | 2017-08-15 00:43:11 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-27 00:16:45 +0200 |
| commit | 1e8635ea0ea370bf4f0f2b2f1b3eb61474dd962a (patch) | |
| tree | 61edf5ee0581762bceb1cc933aa4b62d7c97056b /drivers/gpu/drm/amd/display/include | |
| parent | drm/amd/display: move vm registers to hwsequencer (diff) | |
| download | kernel-qcow2-linux-1e8635ea0ea370bf4f0f2b2f1b3eb61474dd962a.tar.gz kernel-qcow2-linux-1e8635ea0ea370bf4f0f2b2f1b3eb61474dd962a.tar.xz kernel-qcow2-linux-1e8635ea0ea370bf4f0f2b2f1b3eb61474dd962a.zip | |
drm/amd/display: Implement HDMI retimer settings for RV AM4 support.
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 6cdbf84f34e6..92fe00fab87c 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -65,6 +65,7 @@ enum dal_device_type { struct device_id { enum dal_device_type device_type:16; uint32_t enum_id:16; /* 1 based enum */ + uint16_t raw_device_tag; }; struct graphics_object_i2c_info { @@ -264,6 +265,20 @@ struct transmitter_configuration { #define NUMBER_OF_DISP_CLK_VOLTAGE 4 #define NUMBER_OF_AVAILABLE_SCLK 5 +struct i2c_reg_info { + unsigned char i2c_reg_index; + unsigned char i2c_reg_val; +}; + +struct ext_hdmi_settings { + unsigned char slv_addr; + unsigned char reg_num; + struct i2c_reg_info reg_settings[9]; + unsigned char reg_num_6g; + struct i2c_reg_info reg_settings_6g[3]; +}; + + /* V6 */ struct integrated_info { struct clock_voltage_caps { @@ -291,6 +306,8 @@ struct integrated_info { struct graphics_object_id ext_encoder_obj_id; /* XBAR mapping of the PHY channels */ union ddi_channel_mapping channel_mapping; + + unsigned short caps; } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID]; @@ -357,6 +374,27 @@ struct integrated_info { uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms; uint32_t lvds_reserved1; uint32_t lvds_bit_depth_control_val; + //Start from V9 + unsigned char dp0_ext_hdmi_slv_addr; + unsigned char dp0_ext_hdmi_reg_num; + struct i2c_reg_info dp0_ext_hdmi_reg_settings[9]; + unsigned char dp0_ext_hdmi_6g_reg_num; + struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3]; + unsigned char dp1_ext_hdmi_slv_addr; + unsigned char dp1_ext_hdmi_reg_num; + struct i2c_reg_info dp1_ext_hdmi_reg_settings[9]; + unsigned char dp1_ext_hdmi_6g_reg_num; + struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3]; + unsigned char dp2_ext_hdmi_slv_addr; + unsigned char dp2_ext_hdmi_reg_num; + struct i2c_reg_info dp2_ext_hdmi_reg_settings[9]; + unsigned char dp2_ext_hdmi_6g_reg_num; + struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3]; + unsigned char dp3_ext_hdmi_slv_addr; + unsigned char dp3_ext_hdmi_reg_num; + struct i2c_reg_info dp3_ext_hdmi_reg_settings[9]; + unsigned char dp3_ext_hdmi_6g_reg_num; + struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3]; }; /** |