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| author | Rex Zhu | 2017-03-17 09:21:55 +0100 |
|---|---|---|
| committer | Alex Deucher | 2017-03-30 05:54:06 +0200 |
| commit | 1c622002b1aae6bf97be6f3c36203a61d8cc61cb (patch) | |
| tree | db8a0c58a2ac740da1ad731df7e433cf0c27ae0d /drivers/gpu/drm/amd/include/asic_reg | |
| parent | drm/amdgpu: enable GFX/UVD/VCE PG for Bristol (diff) | |
| download | kernel-qcow2-linux-1c622002b1aae6bf97be6f3c36203a61d8cc61cb.tar.gz kernel-qcow2-linux-1c622002b1aae6bf97be6f3c36203a61d8cc61cb.tar.xz kernel-qcow2-linux-1c622002b1aae6bf97be6f3c36203a61d8cc61cb.zip | |
drm/amd/powerplay: add a new register define for APU in VI.
the ixcurrent_pg_status addr is different between APU and DGPU.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h index 4446d43d2a8f..bd3685166779 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_d.h @@ -1272,5 +1272,6 @@ #define ixROM_SW_DATA_63 0xc0600120 #define ixROM_SW_DATA_64 0xc0600124 #define ixCURRENT_PG_STATUS 0xc020029c +#define ixCURRENT_PG_STATUS_APU 0xd020029c #endif /* SMU_7_1_2_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h index 0333d880bc9e..b89347ed1a40 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h @@ -1245,4 +1245,6 @@ #define ixGC_CAC_ACC_CU15 0xc9 #define ixGC_CAC_OVRD_CU 0xe7 #define ixCURRENT_PG_STATUS 0xc020029c +#define ixCURRENT_PG_STATUS_APU 0xd020029c + #endif /* SMU_7_1_3_D_H */ |