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| author | Tom St Denis | 2017-09-06 14:04:10 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-09-12 20:31:02 +0200 |
| commit | 38e40d9cc428eed0795fa5345357f50da4ec0f21 (patch) | |
| tree | 6cb5c74dc7edc09eb9ede2dbcc85c1dad627e79a /drivers/gpu/drm/amd/include/cgs_common.h | |
| parent | drm/amd/powerplay: Simplify vega10_acg_disable() (diff) | |
| download | kernel-qcow2-linux-38e40d9cc428eed0795fa5345357f50da4ec0f21.tar.gz kernel-qcow2-linux-38e40d9cc428eed0795fa5345357f50da4ec0f21.tar.xz kernel-qcow2-linux-38e40d9cc428eed0795fa5345357f50da4ec0f21.zip | |
drm/amd/powerplay: Introduction of bitmask macros for registers
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/cgs_common.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/cgs_common.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h index 0214f63f52fc..92eaa81f9fcb 100644 --- a/drivers/gpu/drm/amd/include/cgs_common.h +++ b/drivers/gpu/drm/amd/include/cgs_common.h @@ -310,6 +310,22 @@ typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, unsigned index, uint32_t value); +#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT +#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK + +#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ + (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ + (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) + +#define CGS_REG_GET_FIELD(value, reg, field) \ + (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD(device, reg, field, val) \ + cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + +#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ + cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) + /** * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) * @cgs_device: opaque device handle |