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| author | Kevin Wang | 2018-12-17 09:47:49 +0100 |
|---|---|---|
| committer | Alex Deucher | 2019-03-19 21:03:56 +0100 |
| commit | 0b51d9937845fb6e0639be2cbd31557c4a36e073 (patch) | |
| tree | d8e12e93a7e1d5300b1c9feed0f94921c3a0d770 /drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | |
| parent | drm/amd/powerplay: implement get_clk_info_from_vbios function for smu11 (v2) (diff) | |
| download | kernel-qcow2-linux-0b51d9937845fb6e0639be2cbd31557c4a36e073.tar.gz kernel-qcow2-linux-0b51d9937845fb6e0639be2cbd31557c4a36e073.tar.xz kernel-qcow2-linux-0b51d9937845fb6e0639be2cbd31557c4a36e073.zip | |
drm/amd/powerplay: implement smu_alloc[free]_memory pool function
This patch implements smu_alloc[free]_memory pool function to reserve the memory
pool bo.
Signed-off-by: Kevin Wang <Kevin1.Wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/amdgpu_smu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 55 |
1 files changed, 54 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index f31b62813256..926d0f87a955 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -137,6 +137,8 @@ static int smu_sw_init(void *handle) if (adev->asic_type < CHIP_VEGA20) return -EINVAL; + smu->pool_size = adev->pm.smu_prv_buffer_size; + ret = smu_init_microcode(smu); if (ret) { pr_err("Failed to load smu firmware!\n"); @@ -333,9 +335,56 @@ static int smu_smc_table_hw_init(struct smu_context *smu) */ static int smu_alloc_memory_pool(struct smu_context *smu) { - return 0; + struct amdgpu_device *adev = smu->adev; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *memory_pool = &smu_table->memory_pool; + uint64_t pool_size = smu->pool_size; + int ret = 0; + + if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) + return ret; + + memory_pool->size = pool_size; + memory_pool->align = PAGE_SIZE; + memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; + + switch (pool_size) { + case SMU_MEMORY_POOL_SIZE_256_MB: + case SMU_MEMORY_POOL_SIZE_512_MB: + case SMU_MEMORY_POOL_SIZE_1_GB: + case SMU_MEMORY_POOL_SIZE_2_GB: + ret = amdgpu_bo_create_kernel(adev, + memory_pool->size, + memory_pool->align, + memory_pool->domain, + &memory_pool->bo, + &memory_pool->mc_address, + &memory_pool->cpu_addr); + break; + default: + break; + } + + return ret; } +static int smu_free_memory_pool(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *memory_pool = &smu_table->memory_pool; + int ret = 0; + + if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) + return ret; + + amdgpu_bo_free_kernel(&memory_pool->bo, + &memory_pool->mc_address, + &memory_pool->cpu_addr); + + memset(memory_pool, 0, sizeof(struct smu_table)); + + return ret; +} static int smu_hw_init(void *handle) { int ret; @@ -399,6 +448,10 @@ static int smu_hw_fini(void *handle) if (ret) return ret; + ret = smu_free_memory_pool(smu); + if (ret) + return ret; + return 0; } |