diff options
| author | Hawking Zhang | 2017-05-23 15:14:19 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-05-25 22:12:27 +0200 |
| commit | efb792c4b2ca0c58c397ed969965d606a73f56bc (patch) | |
| tree | da00f1921f14e1459fcf6e9fb2910edfcc97f028 /drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | |
| parent | drm/amd/powerplay: update magic number for rv hw backend (diff) | |
| download | kernel-qcow2-linux-efb792c4b2ca0c58c397ed969965d606a73f56bc.tar.gz kernel-qcow2-linux-efb792c4b2ca0c58c397ed969965d606a73f56bc.tar.xz kernel-qcow2-linux-efb792c4b2ca0c58c397ed969965d606a73f56bc.zip | |
drm/amd/powerplay: add get_temperature interface for raven
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c index c8b2917b2a2f..6155abead46c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -35,6 +35,7 @@ #include "rv_hwmgr.h" #include "power_state.h" #include "rv_smumgr.h" +#include "pp_soc15.h" #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5 #define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip @@ -42,7 +43,6 @@ #define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz #define SMC_RAM_END 0x40000 - static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic; int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr, struct pp_display_clock_request *clock_req); @@ -613,6 +613,7 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; rv_init_vq_budget_table(hwmgr); + return result; } @@ -981,10 +982,32 @@ static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c return -EINVAL; } +static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr) +{ + uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0, + mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP); + uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset); + int cur_temp = + (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; + + if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) + cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + else + cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return cur_temp; +} + static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { - return -EINVAL; + switch (idx) { + case AMDGPU_PP_SENSOR_GPU_TEMP: + *((uint32_t *)value) = rv_thermal_get_temperature(hwmgr); + return 0; + default: + return -EINVAL; + } } static const struct pp_hwmgr_func rv_hwmgr_funcs = { |