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| author | Rex Zhu | 2018-07-05 13:22:50 +0200 |
|---|---|---|
| committer | Alex Deucher | 2018-08-27 18:09:47 +0200 |
| commit | f688b614b64368ce1681f28cb6f2ff53e1eb8462 (patch) | |
| tree | 4a3b93db51ff3c3a45c66c58836bbd70a292faba /drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | |
| parent | drm/amdgpu: Add job pipe sync dependecy trace (diff) | |
| download | kernel-qcow2-linux-f688b614b64368ce1681f28cb6f2ff53e1eb8462.tar.gz kernel-qcow2-linux-f688b614b64368ce1681f28cb6f2ff53e1eb8462.tar.xz kernel-qcow2-linux-f688b614b64368ce1681f28cb6f2ff53e1eb8462.zip | |
drm/amd/pp: Implement get_performance_level for legacy dgpu
display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management,
so need to add new interface to notify display
the clock info
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 052e60dfaf9f..380f282a64ba 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -5008,6 +5008,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint return 0; } +static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, + PHM_PerformanceLevelDesignation designation, uint32_t index, + PHM_PerformanceLevel *level) +{ + const struct smu7_power_state *ps; + struct smu7_hwmgr *data; + uint32_t i; + + if (level == NULL || hwmgr == NULL || state == NULL) + return -EINVAL; + + data = hwmgr->backend; + ps = cast_const_phw_smu7_power_state(state); + + i = index > ps->performance_level_count - 1 ? + ps->performance_level_count - 1 : index; + + level->coreClock = ps->performance_levels[i].engine_clock; + level->memory_clock = ps->performance_levels[i].memory_clock; + + return 0; +} + static const struct pp_hwmgr_func smu7_hwmgr_funcs = { .backend_init = &smu7_hwmgr_backend_init, .backend_fini = &smu7_hwmgr_backend_fini, @@ -5064,6 +5087,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { .set_power_limit = smu7_set_power_limit, .get_power_profile_mode = smu7_get_power_profile_mode, .set_power_profile_mode = smu7_set_power_profile_mode, + .get_performance_level = smu7_get_performance_level, }; uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, |