diff options
| author | Huang Rui | 2018-12-17 07:56:40 +0100 |
|---|---|---|
| committer | Alex Deucher | 2019-03-19 21:03:56 +0100 |
| commit | 08115f87c38de82f82991a990e36806fa6f3057d (patch) | |
| tree | 106275efe6fcbac58d58255227498e0f12f4c0d2 /drivers/gpu/drm/amd/powerplay/smu_v11_0.c | |
| parent | drm/amd/powerplay: implement get_vbios_bootup_values function for smu11 (v2) (diff) | |
| download | kernel-qcow2-linux-08115f87c38de82f82991a990e36806fa6f3057d.tar.gz kernel-qcow2-linux-08115f87c38de82f82991a990e36806fa6f3057d.tar.xz kernel-qcow2-linux-08115f87c38de82f82991a990e36806fa6f3057d.zip | |
drm/amd/powerplay: implement get_clk_info_from_vbios function for smu11 (v2)
This patch implements the get_clk_info_from_vbios function for smu11.
We can do execute_vbios_cmd_table to fetch the clk value from vbios.
v2: use the proper cpu_to_le[32|16]() and le[32|16]_to_cpu() macros to handle
endianness. (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smu_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index f036313153ae..adae5a70368e 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -30,6 +30,7 @@ #include "smu_v11_0_ppsmc.h" #include "smu11_driver_if.h" #include "soc15_common.h" +#include "atom.h" #include "asic_reg/thm/thm_11_0_2_offset.h" #include "asic_reg/thm/thm_11_0_2_sh_mask.h" @@ -401,6 +402,43 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) return 0; } +static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu) +{ + int ret, index; + struct amdgpu_device *adev = smu->adev; + struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; + struct atom_get_smu_clock_info_output_parameters_v3_1 *output; + + input.clk_id = SMU11_SYSPLL0_SOCCLK_ID; + input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, + getsmuclockinfo); + + ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, + (uint32_t *)&input); + if (ret) + return -EINVAL; + + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; + smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; + + memset(&input, 0, sizeof(input)); + input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID; + input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; + index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1, + getsmuclockinfo); + + ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, + (uint32_t *)&input); + if (ret) + return -EINVAL; + + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; + smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000; + + return 0; +} + static const struct smu_funcs smu_v11_0_funcs = { .init_microcode = smu_v11_0_init_microcode, .load_microcode = smu_v11_0_load_microcode, @@ -414,6 +452,7 @@ static const struct smu_funcs smu_v11_0_funcs = { .init_power = smu_v11_0_init_power, .fini_power = smu_v11_0_fini_power, .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, + .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios, }; void smu_v11_0_set_smu_funcs(struct smu_context *smu) |