diff options
| author | Rex Zhu | 2017-05-10 10:18:34 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-05-24 23:39:40 +0200 |
| commit | 676b4087fcb44f9816eaeb21261ed25dd3f3c822 (patch) | |
| tree | 6c9f9756a022968dad0957442ea8b915367b1745 /drivers/gpu/drm/amd/powerplay | |
| parent | drm/amd/powerplay: fix bug in processing CKS_Enable bit. (diff) | |
| download | kernel-qcow2-linux-676b4087fcb44f9816eaeb21261ed25dd3f3c822.tar.gz kernel-qcow2-linux-676b4087fcb44f9816eaeb21261ed25dd3f3c822.tar.xz kernel-qcow2-linux-676b4087fcb44f9816eaeb21261ed25dd3f3c822.zip | |
drm/amd/powerplay: convert from number of lanes to lane bits on vega10
We need a mask.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewws-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 48803eb2822b..c16c37e42234 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -1170,12 +1170,12 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) bios_pcie_table->entries[i].gen_speed; if (data->registry_data.pcieLaneOverride) - pcie_table->pcie_lane[i] = - data->registry_data.pcieLaneOverride; + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + data->registry_data.pcieLaneOverride); else - pcie_table->pcie_lane[i] = - bios_pcie_table->entries[i].lane_width; - + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + bios_pcie_table->entries[i].lane_width); + printk("pcie_table->pcie_lane[%d] is %d %d\n", i, pcie_table->pcie_lane[i], bios_pcie_table->entries[i].lane_width); if (data->registry_data.pcieClockOverride) pcie_table->lclk[i] = data->registry_data.pcieClockOverride; |