diff options
| author | Jun Lei | 2019-05-22 19:20:34 +0200 |
|---|---|---|
| committer | Alex Deucher | 2019-06-22 16:34:13 +0200 |
| commit | 5d36f78311cfff7ad539fe6200fbb126ca0e92a7 (patch) | |
| tree | 126850e4ff01ed6e0611308ef4749e9be9d1c690 /drivers/gpu/drm/amd | |
| parent | drm/amd/display: update dsc max_target_bpp to 16 bpp (diff) | |
| download | kernel-qcow2-linux-5d36f78311cfff7ad539fe6200fbb126ca0e92a7.tar.gz kernel-qcow2-linux-5d36f78311cfff7ad539fe6200fbb126ca0e92a7.tar.xz kernel-qcow2-linux-5d36f78311cfff7ad539fe6200fbb126ca0e92a7.zip | |
drm/amd/display: making DCN20 WM table non-overlapping
[why]
Existing behavior has overlapping ranges resulting in path
dependent SMU selection
[how]
Make ranges non-overlapping, resulting in non-path dependent
selection
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 310687ec166e..36bf14332bf5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2635,7 +2635,8 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ calculated_states[i].state = i; calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; - min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1008 / 1000000; + // FCLK:UCLK ratio is 1.08 + min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000; calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? min_dcfclk : min_fclk_required_by_uclk; @@ -2989,21 +2990,19 @@ static bool construct( ranges.num_reader_wm_sets = 1; } else if (dcn2_0_soc.num_states > 1) { - for (i = 0; i < 4 && i < dcn2_0_soc.num_states - 1; i++) { + for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) { ranges.reader_wm_sets[i].wm_inst = i; ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; - ranges.reader_wm_sets[i].min_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16; - ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i + 1].dram_speed_mts / 16; + ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; + ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16; ranges.num_reader_wm_sets = i + 1; } - } - ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; - ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; - ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; - ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; + ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + } ranges.num_writer_wm_sets = 1; |