diff options
author | Charlene Liu | 2017-08-01 19:23:56 +0200 |
---|---|---|
committer | Alex Deucher | 2017-09-27 00:16:15 +0200 |
commit | 746e082fdd1c7650322ba4c08652245fcdf83adb (patch) | |
tree | 802cdca56eb59e115854416d028c73d098027363 /drivers/gpu/drm/amd | |
parent | drm/amd/display: Fix comment placement for when new_stream is null (diff) | |
download | kernel-qcow2-linux-746e082fdd1c7650322ba4c08652245fcdf83adb.tar.gz kernel-qcow2-linux-746e082fdd1c7650322ba4c08652245fcdf83adb.tar.xz kernel-qcow2-linux-746e082fdd1c7650322ba4c08652245fcdf83adb.zip |
drm/amd/display: update predefined latency for Rv1_F0
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index ff2dcb7a491d..6006fb4799c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1323,6 +1323,13 @@ static bool construct( dc->dcn_ip = dcn10_ip_defaults; dc->dcn_soc = dcn10_soc_defaults; + if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { + dc->dcn_soc.urgent_latency = 3; + dc->public.debug.disable_dmcu = true; + dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 41.60f; + } + + dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; ASSERT(dc->dcn_soc.number_of_channels < 3); if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/ @@ -1333,6 +1340,9 @@ static bool construct( dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f; dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f; dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f; + if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { + dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 20.80f; + } } if (!dc->public.debug.disable_pplib_clock_request) diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index af9fa66b32b8..14e3146a0cb2 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -115,6 +115,9 @@ #define RAVEN_UNKNOWN 0xFF #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) +#define RAVEN1_F0 0xF0 +#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) + #define FAMILY_RV 142 /* DCN 1*/ |