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author | Alex Deucher | 2018-05-10 21:45:12 +0200 |
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committer | Alex Deucher | 2018-05-24 06:51:20 +0200 |
commit | 99631045862e2994b47285a8cc96bc939ae5b42f (patch) | |
tree | 3666f023ff4a8f29b4b9d8ff2dce828c4b864d5a /drivers/gpu/drm/amd | |
parent | Remove calls to suspend/resume atomic helpers from amdgpu_device_gpu_recover.... (diff) | |
download | kernel-qcow2-linux-99631045862e2994b47285a8cc96bc939ae5b42f.tar.gz kernel-qcow2-linux-99631045862e2994b47285a8cc96bc939ae5b42f.tar.xz kernel-qcow2-linux-99631045862e2994b47285a8cc96bc939ae5b42f.zip |
drm/amdgpu: add new DF 1.7 register defs
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h index 2b305dd021e8..e6044e27a913 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h @@ -30,4 +30,8 @@ #define mmDF_CS_AON0_DramBaseAddress0 0x0044 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0 0x0214 +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX 0 + + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h index 2ba849798924..a78c99480e2d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h @@ -45,4 +45,8 @@ #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L +//DF_CS_AON0_CoherentSlaveModeCtrlA0 +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT 0x3 +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK 0x00000008L + #endif |