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authorRex Zhu2017-09-25 15:18:19 +0200
committerAlex Deucher2017-09-28 22:03:35 +0200
commitce440e3a0caa7580f74aa27e573e1a9777d91522 (patch)
tree1a706705ab39cd9aaaff25fb27089749750d9c6b /drivers/gpu/drm/amd
parentdrm/amdgpu: create powerplay by cgs interface (diff)
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drm/amd/powerplay: change dmesg log level in powerplay
Use pr_debug to prevent spamming unimportant dmesg. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 73bb99d62a44..189f3b54a385 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -704,7 +704,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
clock = hwmgr->display_config.min_core_set_clock;
if (clock == 0)
- pr_info("min_core_set_clock not set\n");
+ pr_debug("min_core_set_clock not set\n");
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
cz_hwmgr->sclk_dpm.hard_min_clk = clock;