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authorAndrzej Hajda2017-02-01 08:47:52 +0100
committerArchit Taneja2017-02-02 10:45:31 +0100
commit45d0ea86d235251305a0e2e63485b08b5caa79e7 (patch)
treec5aec94e594ddad3e453a075d0734931fcd6a7fc /drivers/gpu/drm/bridge
parentdrm/bridge/sii8620: enable MHL3 mode if possible (diff)
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drm/bridge/sii8620: enable interlace modes
Bug in DECON(CRTC) driver prevented interlace modes from proper work. Since DECON is fixed interlace modes can be enabled in MHL. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-26-git-send-email-a.hajda@samsung.com
Diffstat (limited to 'drivers/gpu/drm/bridge')
-rw-r--r--drivers/gpu/drm/bridge/sil-sii8620.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index dae94899ac45..cdd0a9d44ba1 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -2115,9 +2115,6 @@ static bool sii8620_mode_fixup(struct drm_bridge *bridge,
int max_lclk;
bool ret = true;
- if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
- return false;
-
mutex_lock(&ctx->lock);
max_lclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : MHL1_MAX_LCLK;