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| author | Chris Zhong | 2018-02-16 13:09:56 +0100 |
|---|---|---|
| committer | Heiko Stuebner | 2018-03-16 11:51:11 +0100 |
| commit | 0a00ac97d29e65093c0d4c7c4f5827528168b73a (patch) | |
| tree | e5ca8a3c74062072eadba612035bb16a512c4b12 /drivers/gpu/drm/drm_property.c | |
| parent | drm: Reduce object size of DRM_ERROR and DRM_DEBUG uses (diff) | |
| download | kernel-qcow2-linux-0a00ac97d29e65093c0d4c7c4f5827528168b73a.tar.gz kernel-qcow2-linux-0a00ac97d29e65093c0d4c7c4f5827528168b73a.tar.xz kernel-qcow2-linux-0a00ac97d29e65093c0d4c7c4f5827528168b73a.zip | |
drm/rockchip: cdn-dp: remove the DP phy switch
There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
only one PHY can connect to DP controller at one time, the other should
be disconnected. The GRF_SOC_CON26 register has a switch bit to do it,
set this bit means enable PHY 1, clear this bit means enable PHY 0.
If the board has 2 Type-C ports, the DP driver get the phy id from
devm_of_phy_get_by_index, and then control this switch according to
this id. But some others board only has one Type-C port, it may be PHY 0
or PHY 1. The dts node id can not tell us the correct PHY id. Hence move
this switch to PHY driver, the PHY driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
[The phy-changes are in the phy-tree now and the cdn-dp wasn't
enabled at all so far, so this change can go through drm-misc
alone without causing issues when testing drm-misc]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20180216120956.19034-6-enric.balletbo@collabora.com
Diffstat (limited to 'drivers/gpu/drm/drm_property.c')
0 files changed, 0 insertions, 0 deletions