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| author | Stefan Agner | 2016-02-08 21:50:13 +0100 |
|---|---|---|
| committer | Stefan Agner | 2016-05-05 19:09:06 +0200 |
| commit | 2c80661d2ea9bac9bc7ba519097745829add1871 (patch) | |
| tree | ed9ac6fc008fdf8517b240c09d4b2e6ee11d3a12 /drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | |
| parent | drm: introduce bus_flags in drm_display_info (diff) | |
| download | kernel-qcow2-linux-2c80661d2ea9bac9bc7ba519097745829add1871.tar.gz kernel-qcow2-linux-2c80661d2ea9bac9bc7ba519097745829add1871.tar.xz kernel-qcow2-linux-2c80661d2ea9bac9bc7ba519097745829add1871.zip | |
drm/fsl-dcu: use bus_flags for pixel clock polarity
The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.
This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h')
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h index 5bb7c261fe95..c275f900ff23 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h @@ -47,8 +47,8 @@ #define DCU_VSYN_PARA_FP(x) (x) #define DCU_SYN_POL 0x0024 -#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) -#define DCU_SYN_POL_NEG_REMAIN (0 << 5) +#define DCU_SYN_POL_INV_PXCK BIT(6) +#define DCU_SYN_POL_NEG BIT(5) #define DCU_SYN_POL_INV_VS_LOW BIT(1) #define DCU_SYN_POL_INV_HS_LOW BIT(0) |