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authorZhao Yakui2012-08-08 15:53:48 +0200
committerDave Airlie2012-08-24 01:28:58 +0200
commitd66760962d75af12697d5197b3e97d51fe64169c (patch)
tree8fe91ce6d5592b3ecf9e1327d5d442d5b6a37224 /drivers/gpu/drm/gma500/psb_intel_drv.h
parentgma500: Fix incorrect SR issue when disabling CRTC already in disabled state (diff)
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gma500: Program the DPLL lane based on the selected digitial port
Based on the spec, the CRT output doesn't use the lane. And the HDMI B output uses the Lane0/1 while the HDMI C output uses the Lane 2/3. But currently it will program all the four lanes for the CRT/HDMI. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> [Ported to the in-kernel driver] Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_intel_drv.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_drv.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h
index ebe1a28f60e1..7b357b04d4e2 100644
--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
@@ -133,6 +133,11 @@ struct psb_intel_encoder {
void (*hot_plug)(struct psb_intel_encoder *);
int crtc_mask;
int clone_mask;
+ u32 ddi_select; /* Channel info */
+#define DDI0_SELECT 0x01
+#define DDI1_SELECT 0x02
+#define DP_MASK 0x8000;
+#define DDI_MASK 0x03
void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */
/* FIXME: Either make SDVO and LVDS store it's i2c here or give CDV it's