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| author | Xinyun Liu | 2018-10-29 07:18:25 +0100 |
|---|---|---|
| committer | Zhenyu Wang | 2018-11-12 10:05:39 +0100 |
| commit | def40774f63ad446aaf5c12e2185045979c06c75 (patch) | |
| tree | cbe8b7f6cec5023f90d376e9035a8d49a5dd6176 /drivers/gpu/drm/i915/gvt | |
| parent | drm/i915/gvt: Handle values of EDP_PSR_IMR and EDP_PSR_IIR (diff) | |
| download | kernel-qcow2-linux-def40774f63ad446aaf5c12e2185045979c06c75.tar.gz kernel-qcow2-linux-def40774f63ad446aaf5c12e2185045979c06c75.tar.xz kernel-qcow2-linux-def40774f63ad446aaf5c12e2185045979c06c75.zip | |
drm/i915/gvt: not to touch undefined MOCS registers
Some engines are not available for all Gens. eg, Gen11 introduced
VCS3/VCS4/VECS2, and VCS2 is not supported on some Gen9 machines. So need to
add check before access them.
Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Signed-off-by: Yakui Zhao <Yakui.Zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/mmio_context.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 088a62ab2bc8..cdd366d44938 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -171,6 +171,8 @@ static void load_render_mocs(struct drm_i915_private *dev_priv) int ring_id, i; for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) { + if (!HAS_ENGINE(dev_priv, ring_id)) + continue; offset.reg = regs[ring_id]; for (i = 0; i < GEN9_MOCS_SIZE; i++) { gen9_render_mocs.control_table[ring_id][i] = |