diff options
author | Paulo Zanoni | 2014-08-21 22:09:38 +0200 |
---|---|---|
committer | Daniel Vetter | 2014-09-03 11:04:23 +0200 |
commit | c8a0bd42df69fe76646b45dea04c7cf4995fa6a3 (patch) | |
tree | 208cf44ab0e6e0c40261609881ace781d8dddaa6 /drivers/gpu/drm/i915/i915_debugfs.c | |
parent | drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating (diff) | |
download | kernel-qcow2-linux-c8a0bd42df69fe76646b45dea04c7cf4995fa6a3.tar.gz kernel-qcow2-linux-c8a0bd42df69fe76646b45dea04c7cf4995fa6a3.tar.xz kernel-qcow2-linux-c8a0bd42df69fe76646b45dea04c7cf4995fa6a3.zip |
drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspend
On BDW we're seeing a problem that after we runtime resume, the
outputs connected to DDI C are not detected: they don't appear in the
SDEISR register and GMBUS transactions don't work. They stop working
at the moment we call intel_opregion_notify_adapter() during runtime
suspend, but they don't go back to work when we call the same function
during runtime resume. They only work after we do a modeset and call
intel_opregion_notify_encoder(), but this point is already too late.
While debugging, I tried to pass PCI_D3hot which is the value that
matches the spec, and it seems to have solved the problem. I couldn't
find any explanation of why this solves the problem, but there's also
no documented explanation - besides our code and git log - of why
Haswell should use PCI_D1, so keep this for now in order to keep BDW
runtime PM working.
Also add a comment to point the fact that there's no spec documenting
all the weirdness involved here.
Cc: kristen.c.accardi@intel.com
Testcase: igt/pm_rpm/drm-resources-equal
Testcase: igt/pm_rpm/i2c
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
0 files changed, 0 insertions, 0 deletions