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| author | Imre Deak | 2016-04-20 19:27:57 +0200 |
|---|---|---|
| committer | Imre Deak | 2016-04-22 14:12:05 +0200 |
| commit | f62c79b33ff150da40fcdfc8cd48d0dd77f62902 (patch) | |
| tree | 5d9941fe3511347de01a645e74a3efcbe636250b /drivers/gpu/drm/i915/i915_drv.c | |
| parent | drm/i915/bxt: Sanitize DC state tracking during system resume (diff) | |
| download | kernel-qcow2-linux-f62c79b33ff150da40fcdfc8cd48d0dd77f62902.tar.gz kernel-qcow2-linux-f62c79b33ff150da40fcdfc8cd48d0dd77f62902.tar.xz kernel-qcow2-linux-f62c79b33ff150da40fcdfc8cd48d0dd77f62902.zip | |
drm/i915/bxt: Enable DC5 during runtime resume
Right after runtime resume we know that we can re-enable DC5, since we
just disabled DC9 and power well 2 is disabled. So enable DC5 explicitly
instead of delaying this until the next time we disable power well 2.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461173277-16090-5-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a0f8913a76f8..7a0e4d6c71e2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1601,6 +1601,9 @@ static int intel_runtime_resume(struct device *device) if (IS_BROXTON(dev)) { bxt_disable_dc9(dev_priv); bxt_display_core_init(dev_priv, true); + if (dev_priv->csr.dmc_payload && + (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) + gen9_enable_dc5(dev_priv); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { hsw_disable_pc8(dev_priv); } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |