diff options
| author | Ben Widawsky | 2013-09-20 18:35:30 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-10-01 07:45:12 +0200 |
| commit | 18b5992c37560dffc52b84dec7f83738847cf5c7 (patch) | |
| tree | f4942bc743519306af364d2d154e3e7ab3786ed6 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | drm/i915/dp: read DPCD PSR capability only on eDP (diff) | |
| download | kernel-qcow2-linux-18b5992c37560dffc52b84dec7f83738847cf5c7.tar.gz kernel-qcow2-linux-18b5992c37560dffc52b84dec7f83738847cf5c7.tar.xz kernel-qcow2-linux-18b5992c37560dffc52b84dec7f83738847cf5c7.zip | |
drm/i915: Calculate PSR register offsets from base + gen
Future generations will be changing these registers (thanks to design
for giving us an early heads up). To help abstract, create the
definition of the base of the register block, and define all registers
relative to that.
Design has promised to not change the offsets relative to the base.
v2: Also change IS_HASWELL checks to HAS_PSR
CC: Rodrigo Vivi <rodrigo.vivi@gmail.com>
CC: Intel GFX <intel-gfx@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 07de53c40e57..bbe889dfc0ff 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1684,6 +1684,7 @@ struct drm_i915_file_private { #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) +#define HAS_PSR(dev) (IS_HASWELL(dev)) #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |