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| author | Ben Widawsky | 2013-07-04 20:02:04 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-07-16 08:00:52 +0200 |
| commit | 05e21cc43da5a1a58b34a2cfad13d22bcfeb1f2b (patch) | |
| tree | 4c1feabc9ece2b2566f3d0d52d1fc56575f96e5b /drivers/gpu/drm/i915/i915_gem.c | |
| parent | drm/i915/hsw: Set correct Haswell PTE encodings. (diff) | |
| download | kernel-qcow2-linux-05e21cc43da5a1a58b34a2cfad13d22bcfeb1f2b.tar.gz kernel-qcow2-linux-05e21cc43da5a1a58b34a2cfad13d22bcfeb1f2b.tar.xz kernel-qcow2-linux-05e21cc43da5a1a58b34a2cfad13d22bcfeb1f2b.zip | |
drm/i915: Define some of the eLLC magic
The EDRAM present register isn't really defined in the docs. It just
says check to see if it's set to 1. So I haven't defined the 1 value not
knowing what it actually means.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 20b10a0fa452..1246dfd5ff92 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4147,8 +4147,8 @@ i915_gem_init_hw(struct drm_device *dev) if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) return -EIO; - if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) - I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); + if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) + I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (HAS_PCH_NOP(dev)) { u32 temp = I915_READ(GEN7_MSG_CTL); |