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| author | Daniel Vetter | 2010-02-01 13:59:16 +0100 |
|---|---|---|
| committer | Eric Anholt | 2010-02-22 17:54:41 +0100 |
| commit | 4a7266123fce399f695b62b7f87b467b317f1487 (patch) | |
| tree | d3341f3552d1c78069c88af26762f49ae7a3ff19 /drivers/gpu/drm/i915/i915_gem.c | |
| parent | agp/intel: official names for Pineview and Ironlake (diff) | |
| download | kernel-qcow2-linux-4a7266123fce399f695b62b7f87b467b317f1487.tar.gz kernel-qcow2-linux-4a7266123fce399f695b62b7f87b467b317f1487.tar.xz kernel-qcow2-linux-4a7266123fce399f695b62b7f87b467b317f1487.zip | |
drm/i915: move a gtt flush to the correct place
No functional change, because gtt flushing is a no-op. Still, try
to keep the bookkeeping accurate. The if is still slightly wrong
for with execbuf2 even i915-class hw doesn't always need a fence
reg for gpu access. But that's for somewhen lateron.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 4a141993a37a..a236bfb30844 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2552,12 +2552,12 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj) int ret; i915_gem_object_flush_gpu_write_domain(obj); - i915_gem_object_flush_gtt_write_domain(obj); ret = i915_gem_object_wait_rendering(obj); if (ret != 0) return ret; } + i915_gem_object_flush_gtt_write_domain(obj); i915_gem_clear_fence_reg (obj); return 0; |