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| author | Chris Wilson | 2017-01-10 15:47:34 +0100 |
|---|---|---|
| committer | Chris Wilson | 2017-01-10 21:54:32 +0100 |
| commit | f51455d442c0fa97e4600960f19bf23b66f0b386 (patch) | |
| tree | bbe0a09197a72cec73e5e8ce867067f693a8f6dd /drivers/gpu/drm/i915/i915_gem_fence_reg.c | |
| parent | drm/i915: Rename i915_gem_engine_cleanup() to engine_set_wedged() (diff) | |
| download | kernel-qcow2-linux-f51455d442c0fa97e4600960f19bf23b66f0b386.tar.gz kernel-qcow2-linux-f51455d442c0fa97e4600960f19bf23b66f0b386.tar.xz kernel-qcow2-linux-f51455d442c0fa97e4600960f19bf23b66f0b386.zip | |
drm/i915: Replace 4096 with PAGE_SIZE or I915_GTT_PAGE_SIZE
Start converting over from the byte count to its semantic macro, either
we want to allocate the size of a physical page in main memory or we
want the size of a virtual page in the GTT. 4096 could mean either, but
PAGE_SIZE and I915_GTT_PAGE_SIZE are explicit and should help improve
code comprehension and future changes. In the future, we may want to use
variable GTT page sizes and so have the challenge of knowing which
hardcoded values were used to represent a physical page vs the virtual
page.
v2: Look for a few more 4096s to convert, discover IS_ALIGNED().
v3: 4096ul paranoia, make fence alignment a distinct value of 4096, keep
bdw stolen w/a as 4096 until we know better.
v4: Add asserts that i915_vma_insert() start/end are aligned to GTT page
sizes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170110144734.26052-1-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_fence_reg.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_fence_reg.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 9e65696a960c..fadbe8f4c745 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -80,11 +80,11 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, unsigned int stride = i915_gem_object_get_stride(vma->obj); GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma)); - GEM_BUG_ON(vma->node.start & 4095); - GEM_BUG_ON(vma->fence_size & 4095); - GEM_BUG_ON(stride & 127); + GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE)); + GEM_BUG_ON(!IS_ALIGNED(vma->fence_size, I965_FENCE_PAGE)); + GEM_BUG_ON(!IS_ALIGNED(stride, 128)); - val = (vma->node.start + vma->fence_size - 4096) << 32; + val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32; val |= vma->node.start; val |= (u64)((stride / 128) - 1) << fence_pitch_shift; if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y) @@ -127,7 +127,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *fence, GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma)); GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK); GEM_BUG_ON(!is_power_of_2(vma->fence_size)); - GEM_BUG_ON(vma->node.start & (vma->fence_size - 1)); + GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size)); if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence->i915)) stride /= 128; @@ -166,7 +166,7 @@ static void i830_write_fence_reg(struct drm_i915_fence_reg *fence, GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK); GEM_BUG_ON(!is_power_of_2(vma->fence_size)); GEM_BUG_ON(!is_power_of_2(stride / 128)); - GEM_BUG_ON(vma->node.start & (vma->fence_size - 1)); + GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size)); val = vma->node.start; if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y) |