diff options
| author | Tvrtko Ursulin | 2016-10-14 10:17:22 +0200 |
|---|---|---|
| committer | Tvrtko Ursulin | 2016-10-14 13:23:19 +0200 |
| commit | 55b8f2a76dff09e0972c93de57cd507ba6237020 (patch) | |
| tree | 53832e7d285ff78fbc5a5f3b69e48667f705ca56 /drivers/gpu/drm/i915/i915_gem_render_state.c | |
| parent | drm/i915: Make IS_VALLEYVIEW only take dev_priv (diff) | |
| download | kernel-qcow2-linux-55b8f2a76dff09e0972c93de57cd507ba6237020.tar.gz kernel-qcow2-linux-55b8f2a76dff09e0972c93de57cd507ba6237020.tar.xz kernel-qcow2-linux-55b8f2a76dff09e0972c93de57cd507ba6237020.zip | |
drm/i915: Make INTEL_GEN only take dev_priv
Saves 968 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
v3: Rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_render_state.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_render_state.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 95b7e9afd5f8..a98c0f42badd 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -72,9 +72,9 @@ render_state_get_rodata(const struct drm_i915_gem_request *req) static int render_state_setup(struct render_state *so) { - struct drm_device *dev = so->vma->vm->dev; + struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev); const struct intel_renderstate_rodata *rodata = so->rodata; - const bool has_64bit_reloc = INTEL_GEN(dev) >= 8; + const bool has_64bit_reloc = INTEL_GEN(dev_priv) >= 8; unsigned int i = 0, reloc_index = 0; struct page *page; u32 *d; @@ -115,7 +115,7 @@ static int render_state_setup(struct render_state *so) so->aux_batch_offset = i * sizeof(u32); - if (HAS_POOLED_EU(dev)) { + if (HAS_POOLED_EU(dev_priv)) { /* * We always program 3x6 pool config but depending upon which * subslice is disabled HW drops down to appropriate config |