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| author | Chris Wilson | 2016-08-15 11:48:54 +0200 |
|---|---|---|
| committer | Chris Wilson | 2016-08-15 12:01:02 +0200 |
| commit | bf3783e52a8929c738c5c8c5fa1df7e267b5271d (patch) | |
| tree | d33da6e8bd47be851a37079cea283ae0900ac025 /drivers/gpu/drm/i915/i915_guc_submission.c | |
| parent | drm/i915: Use VMA directly for checking tiling parameters (diff) | |
| download | kernel-qcow2-linux-bf3783e52a8929c738c5c8c5fa1df7e267b5271d.tar.gz kernel-qcow2-linux-bf3783e52a8929c738c5c8c5fa1df7e267b5271d.tar.xz kernel-qcow2-linux-bf3783e52a8929c738c5c8c5fa1df7e267b5271d.zip | |
drm/i915: Use VMA as the primary object for context state
When working with contexts, we most frequently want the GGTT VMA for the
context state, first and foremost. Since the object is available via the
VMA, we need only then store the VMA.
v2: Formatting tweaks to debugfs output, restored some comments removed
in the next patch
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471254551-25805-15-git-send-email-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/i915_guc_submission.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_guc_submission.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 29de8cec1b58..4f0f173f9754 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -358,7 +358,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc, lrc->context_desc = lower_32_bits(ce->lrc_desc); /* The state page is after PPHWSP */ - gfx_addr = i915_gem_obj_ggtt_offset(ce->state); + gfx_addr = ce->state->node.start; lrc->ring_lcra = gfx_addr + LRC_STATE_PN * PAGE_SIZE; lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | (guc_engine_id << GUC_ELC_ENGINE_OFFSET); @@ -1080,7 +1080,7 @@ int intel_guc_suspend(struct drm_device *dev) /* any value greater than GUC_POWER_D0 */ data[1] = GUC_POWER_D1; /* first page is shared data with GuC */ - data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); + data[2] = ctx->engine[RCS].state->node.start; return host2guc_action(guc, data, ARRAY_SIZE(data)); } @@ -1105,7 +1105,7 @@ int intel_guc_resume(struct drm_device *dev) data[0] = HOST2GUC_ACTION_EXIT_S_STATE; data[1] = GUC_POWER_D0; /* first page is shared data with GuC */ - data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); + data[2] = ctx->engine[RCS].state->node.start; return host2guc_action(guc, data, ARRAY_SIZE(data)); } |