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| author | Dhinakaran Pandiyan | 2018-08-22 00:11:56 +0200 |
|---|---|---|
| committer | Dhinakaran Pandiyan | 2018-08-22 02:55:11 +0200 |
| commit | 1aeb1b5fa069f7d7a0de3ac8a33547014613fc7a (patch) | |
| tree | 2f027e6767af89738f6b43627910b52a36b5fe6e /drivers/gpu/drm/i915/i915_irq.c | |
| parent | drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit (diff) | |
| download | kernel-qcow2-linux-1aeb1b5fa069f7d7a0de3ac8a33547014613fc7a.tar.gz kernel-qcow2-linux-1aeb1b5fa069f7d7a0de3ac8a33547014613fc7a.tar.xz kernel-qcow2-linux-1aeb1b5fa069f7d7a0de3ac8a33547014613fc7a.zip | |
drm/i915/psr: Mask PSR irq bits when re-enabling interrupts.
gen8_de_irq_postinstall() wasn't masking the IRQ bit before passing the
debug flag to psr_irq_control(). This check was missed when new debug bits
were defined in 'commit c44301fce614 ("drm/i915: Allow control of PSR at
runtime through debugfs, v6")'. Instead of ANDing the irq bit in all the
callers, move it to the callee.
v2: Rebased.
Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through
debugfs, v6")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180821221156.2442-3-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b2c9838442bc..8084e35b25c5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) if (IS_HASWELL(dev_priv)) { gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); - intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ); + intel_psr_irq_control(dev_priv, dev_priv->psr.debug); display_mask |= DE_EDP_PSR_INT_HSW; } |