diff options
| author | Ville Syrjälä | 2014-10-16 19:52:32 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2014-10-24 16:34:11 +0200 |
| commit | 142d2eca356af6744c7e4bb577c3dfaadee486fc (patch) | |
| tree | 743a2c3a551483bf5908e849631aa921f30bc29d /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Don't claim that we're resetting PCH ADPA register (diff) | |
| download | kernel-qcow2-linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.tar.gz kernel-qcow2-linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.tar.xz kernel-qcow2-linux-142d2eca356af6744c7e4bb577c3dfaadee486fc.zip | |
drm/i915: Fix chv PCS DW11 register defines
I managed to fumble the per spline PCS DW11 register defines in:
commit 570e2a747bc06cd8620662c5125ec2dc964c511b
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Mon Aug 18 14:42:46 2014 +0300
drm/i915: Clear TX FIFO reset master override bits on chv
Fortunately the bit in DW0 that was cleared due to this didn't have
any effect as long as the bit we meant to clear was already zero.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Fix commit ref as pointed out by Jani.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6db369a91ee9..46cfbc7466ef 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -883,8 +883,8 @@ enum punit_power_well { #define _VLV_PCS23_DW11_CH0 0x042c #define _VLV_PCS01_DW11_CH1 0x262c #define _VLV_PCS23_DW11_CH1 0x282c -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) +#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) +#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) #define _VLV_PCS_DW12_CH0 0x8230 #define _VLV_PCS_DW12_CH1 0x8430 |