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| author | Ben Widawsky | 2013-11-03 05:07:47 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2013-11-08 18:09:59 +0100 |
| commit | 2a114cc1b964ba0208aa6858d01cee82ac026ec6 (patch) | |
| tree | 36a8d874e57fd4d864d3956735c872b3de3b1b86 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/bdw: Add Broadwell display FIFO limits (diff) | |
| download | kernel-qcow2-linux-2a114cc1b964ba0208aa6858d01cee82ac026ec6.tar.gz kernel-qcow2-linux-2a114cc1b964ba0208aa6858d01cee82ac026ec6.tar.xz kernel-qcow2-linux-2a114cc1b964ba0208aa6858d01cee82ac026ec6.zip | |
drm/i915/bdw: Use The GT mailbox for IPS enable/disable
v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2abdd78fdef..f99c8c5b7bd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4953,6 +4953,7 @@ #define GEN6_PCODE_WRITE_D_COMP 0x11 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) +#define DISPLAY_IPS_CONTROL 0x19 #define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |