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| author | Ville Syrjälä | 2015-05-22 10:22:33 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-05-29 10:15:28 +0200 |
| commit | 34edce2fea6960ce5855d6e09902f82822c374c5 (patch) | |
| tree | 2b40d0b590809837df3aaec1ec630aa80240495f /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Fix 852GM/GMV cdclk (diff) | |
| download | kernel-qcow2-linux-34edce2fea6960ce5855d6e09902f82822c374c5.tar.gz kernel-qcow2-linux-34edce2fea6960ce5855d6e09902f82822c374c5.tar.xz kernel-qcow2-linux-34edce2fea6960ce5855d6e09902f82822c374c5.zip | |
drm/i915: Add cdclk extraction for g33, g965gm and g4x
Implement cdclk extraction for g33, 965gm and g4x platforms. The details
came from configdb. Sadly there isn't anything there for other gen3/gen4
chipsets.
So far I've tested this on one ELK where it gave me a HPLL VCO of 5333
MHz and cdclk of 444 MHz which seems perfectly sane for this machine.
v2: Rebased to the latest
v3: Rebased to the latest
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a2daf599c97d..00cec1f70b64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2493,6 +2493,9 @@ enum skl_disp_power_wells { #define CLKCFG_MEM_800 (3 << 4) #define CLKCFG_MEM_MASK (7 << 4) +#define HPLLVCO (MCHBAR_MIRROR_BASE + 0xc38) +#define HPLLVCO_MOBILE (MCHBAR_MIRROR_BASE + 0xc0f) + #define TSC1 0x11001 #define TSE (1<<0) #define TR1 0x11006 |