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| author | Ville Syrjälä | 2015-11-04 22:20:10 +0100 |
|---|---|---|
| committer | Ville Syrjälä | 2015-11-18 13:35:36 +0100 |
| commit | 35dc3f97a69bb344768c6a2f47da2be46b11645a (patch) | |
| tree | 0ef4a4a9adc9f7d6c8cb2d9cb787188a50744b7e /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Wrap ASSIGN_CTX_{PDP,PM4L} in do {} while(0) (diff) | |
| download | kernel-qcow2-linux-35dc3f97a69bb344768c6a2f47da2be46b11645a.tar.gz kernel-qcow2-linux-35dc3f97a69bb344768c6a2f47da2be46b11645a.tar.xz kernel-qcow2-linux-35dc3f97a69bb344768c6a2f47da2be46b11645a.zip | |
drm/i915: Give names to more ring registers
The logical render context population has a bunch of raw ring register
offsets. Use the names we have for them, and in cases where we we don't,
give them names.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-23-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b24d02fbc126..fd810679070e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1653,8 +1653,16 @@ enum skl_disp_power_wells { #define HWSTAM 0x02098 #define DMA_FADD_I8XX 0x020d0 #define RING_BBSTATE(base) ((base)+0x110) +#define RING_BB_PPGTT (1 << 5) +#define RING_SBBADDR(base) ((base)+0x114) /* hsw+ */ +#define RING_SBBSTATE(base) ((base)+0x118) /* hsw+ */ +#define RING_SBBADDR_UDW(base) ((base)+0x11c) /* gen8+ */ #define RING_BBADDR(base) ((base)+0x140) #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ +#define RING_BB_PER_CTX_PTR(base) ((base)+0x1c0) /* gen8+ */ +#define RING_INDIRECT_CTX(base) ((base)+0x1c4) /* gen8+ */ +#define RING_INDIRECT_CTX_OFFSET(base) ((base)+0x1c8) /* gen8+ */ +#define RING_CTX_TIMESTAMP(base) ((base)+0x3a8) /* gen8+ */ #define ERROR_GEN6 0x040a0 #define GEN7_ERR_INT 0x44040 |