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| author | Paulo Zanoni | 2013-05-31 21:33:22 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2013-05-31 21:39:55 +0200 |
| commit | 42db64efcd95014570835c7b0a08277c60486f07 (patch) | |
| tree | fecea5bb8b671eeaeadbf5df38559e89dc451cbe /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: fix up the edp power well check (diff) | |
| download | kernel-qcow2-linux-42db64efcd95014570835c7b0a08277c60486f07.tar.gz kernel-qcow2-linux-42db64efcd95014570835c7b0a08277c60486f07.tar.xz kernel-qcow2-linux-42db64efcd95014570835c7b0a08277c60486f07.zip | |
drm/i915: implement IPS feature
Intermediate Pixel Storage is a feature that should reduce the number
of times the display engine wakes up memory to read pixels, so it
should allow deeper PC states. IPS can only be enabled on ULT pipe A
with 8:8:8 pipe pixel formats.
With eDP 1920x1080 and correct watermarks but without FBC this moves
my PC7 residency from 2.5% to around 38%.
v2: - It's tied to pipe A, not port A
- Add pipe_config support (Chris)
- Add some assertions (Chris)
- Rebase against latest dinq
v3: - Don't ever set ips_enabled to false (Daniel)
- Only check for ips_enabled at hsw_disable_ips (Daniel)
v4: - Add hsw_compute_ips_config (Daniel)
- Use the new dump_pipe_config (Daniel)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 89fac19d3249..5a593d20036c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1023,6 +1023,8 @@ /* Framebuffer compression for Ivybridge */ #define IVB_FBC_RT_BASE 0x7020 +#define IPS_CTL 0x43408 +#define IPS_ENABLE (1 << 31) #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 @@ -3666,6 +3668,15 @@ #define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) +#define _GAMMA_MODE_A 0x4a480 +#define _GAMMA_MODE_B 0x4ac80 +#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define GAMMA_MODE_MODE_MASK (3 << 0) +#define GAMMA_MODE_MODE_8bit (0 << 0) +#define GAMMA_MODE_MODE_10bit (1 << 0) +#define GAMMA_MODE_MODE_12bit (2 << 0) +#define GAMMA_MODE_MODE_SPLIT (3 << 0) + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29) |