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| author | Armin Reese | 2012-03-31 01:20:16 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-04-17 17:54:51 +0200 |
| commit | 446f254566ea8911c9e19c7bc8a162fc0e53cf31 (patch) | |
| tree | 22c60cf8cf85a7e87676780faeca086dafbb2596 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: disable rc6 on haswell for now (diff) | |
| download | kernel-qcow2-linux-446f254566ea8911c9e19c7bc8a162fc0e53cf31.tar.gz kernel-qcow2-linux-446f254566ea8911c9e19c7bc8a162fc0e53cf31.tar.xz kernel-qcow2-linux-446f254566ea8911c9e19c7bc8a162fc0e53cf31.zip | |
drm/i915: Mask reserved bits in display/sprite address registers
The purpose of this patch is to avoid zeroing the lower 12 reserved bits
of surface base address registers (framebuffer & sprite). There are bits
in that range that may occasionally be set by BIOS or by other components.
Signed-off-by: Armin Reese <armin.c.reese@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0668815d05d7..d093dba8224b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2869,6 +2869,13 @@ #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) +/* Display/Sprite base address macros */ +#define DISP_BASEADDR_MASK (0xfffff000) +#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) +#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) +#define I915_MODIFY_DISPBASE(reg, gfx_addr) \ + (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) + /* VBIOS flags */ #define SWF00 0x71410 #define SWF01 0x71414 |