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| author | Eugeni Dodonov | 2012-03-29 17:32:36 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2012-04-09 18:04:04 +0200 |
| commit | 4dffc4043a392b4a0f13f033330d31833bbf9f35 (patch) | |
| tree | c09663d2e291b26352eae5dec98982c9c4eefe71 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: add LCPLL control registers (diff) | |
| download | kernel-qcow2-linux-4dffc4043a392b4a0f13f033330d31833bbf9f35.tar.gz kernel-qcow2-linux-4dffc4043a392b4a0f13f033330d31833bbf9f35.tar.xz kernel-qcow2-linux-4dffc4043a392b4a0f13f033330d31833bbf9f35.zip | |
drm/i915: add WRPLL clocks
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP
and FDI.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8c44fe0b4fa4..fa4d1d303623 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4157,6 +4157,14 @@ #define SPLL_PLL_FREQ_810MHz (0<<26) #define SPLL_PLL_FREQ_1350MHz (1<<26) +/* WRPLL */ +#define WRPLL_CTL1 0x46040 +#define WRPLL_CTL2 0x46060 +#define WRPLL_PLL_ENABLE (1<<31) +#define WRPLL_PLL_SELECT_SSC (0x01<<28) +#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) +#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) + /* Port clock selection */ #define PORT_CLK_SEL_A 0x46100 #define PORT_CLK_SEL_B 0x46104 |