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| author | Satheeshakrishna M | 2014-11-13 15:55:16 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2014-11-14 11:18:13 +0100 |
| commit | 540e732c8e2d90a18c9a7798451c2cdf78b9acb6 (patch) | |
| tree | 0480857ae9232779f07af7f309e6ffcaee0bcfa0 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915/skl: CD clock back calculation for SKL (diff) | |
| download | kernel-qcow2-linux-540e732c8e2d90a18c9a7798451c2cdf78b9acb6.tar.gz kernel-qcow2-linux-540e732c8e2d90a18c9a7798451c2cdf78b9acb6.tar.xz kernel-qcow2-linux-540e732c8e2d90a18c9a7798451c2cdf78b9acb6.zip | |
drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock
v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum.
And add a fixme about the abuse of pipe_config here.
v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien)
v4: Modified as per review comments from Paulo
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba7815d7881e..c443008e99d8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6453,6 +6453,7 @@ enum punit_power_well { #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) +#define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) #define DPLL_CRTL1_LINK_RATE_2700 0 @@ -6466,6 +6467,7 @@ enum punit_power_well { #define DPLL_CTRL2 0x6C05C #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) +#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) @@ -6502,6 +6504,9 @@ enum punit_power_well { #define DPLL_CFGCR2_PDIV_7 (4<<2) #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) +#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) +#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) + /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, * since on HSW we can't write to it using I915_WRITE. */ #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) |