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authorChristian Schmidt2011-12-19 20:03:33 +0100
committerDave Airlie2011-12-20 10:51:23 +0100
commit59df7b1771c150163e522f33c638096ab0efbf42 (patch)
tree4109cb8f5934d87bf7f875a9f9f0cbb901d41c42 /drivers/gpu/drm/i915/i915_reg.h
parentFix wrong assumptions in cea_for_each_detailed_block v2 (diff)
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drm/intel: Fix initialization if startup happens in interlaced mode [v2]
My EFI BIOS starts the graphics card up in my projector's preferred EDID mode, 1080@60i. The Intel driver does not clear all the interlaced bits. This patch introduces a new PIPECONF_INTERLACE_MASK define and uses it to restore progressive mode. Signed-of-by: Christian Schmidt <schmidt@digadd.de> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a09416e611f..517bf0cda3e5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2312,6 +2312,7 @@
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
+#define PIPECONF_INTERLACE_MASK (7 << 21)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_BPP_MASK (0x000000e0)
#define PIPECONF_BPP_8 (0<<5)