diff options
| author | Ville Syrjälä | 2015-06-29 14:25:49 +0200 |
|---|---|---|
| committer | Daniel Vetter | 2015-07-13 10:41:33 +0200 |
| commit | 60bfe44f83c0a9d7293e821c4ddae3770d60acf9 (patch) | |
| tree | 4ec7146d1ad20b3b5aa1f614e5873b0da486f53c /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Keep GMCH DPLL VGA mode always disabled (diff) | |
| download | kernel-qcow2-linux-60bfe44f83c0a9d7293e821c4ddae3770d60acf9.tar.gz kernel-qcow2-linux-60bfe44f83c0a9d7293e821c4ddae3770d60acf9.tar.xz kernel-qcow2-linux-60bfe44f83c0a9d7293e821c4ddae3770d60acf9.zip | |
drm/i915: Apply OCD to VLV/CHV DPLL defines
Drop the spurious 'A' from the VLV/CHV ref clock enable define,
and add the "REF" to the VLV ref clock selection bit. Also
s/CLOCK/CLK/ for extra consistency.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1c4d7894b429..0650a3d8a40f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2150,7 +2150,7 @@ enum skl_disp_power_wells { #define DPLL_DVO_2X_MODE (1 << 30) #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) #define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) +#define DPLL_REF_CLK_ENABLE_VLV (1 << 29) #define DPLL_VGA_MODE_DIS (1 << 28) #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ @@ -2164,8 +2164,8 @@ enum skl_disp_power_wells { #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ #define DPLL_LOCK_VLV (1<<15) #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) -#define DPLL_INTEGRATED_CLOCK_VLV (1<<13) -#define DPLL_SSC_REF_CLOCK_CHV (1<<13) +#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13) +#define DPLL_SSC_REF_CLK_CHV (1<<13) #define DPLL_PORTC_READY_MASK (0xf << 4) #define DPLL_PORTB_READY_MASK (0xf) |